Layout Optimization in VLSI Design

Layout Optimization in VLSI Design edited by Bing Lu, Ding-Zhu Du, S. Sapatnekar.

Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter­ connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form th...

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Bibliographic Details
Corporate Author: SpringerLink (Online service)
Other Authors: Bing Lu (Editor), Ding-Zhu Du (Editor), Sapatnekar, S. (Editor)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 2001.
Edition:1st ed. 2001.
Series:Network Theory and Applications, 8
Springer eBook Collection.
Subjects:
Computer simulation.
Computers.
Electronic circuits.
Computer-aided engineering.
Electrical engineering.
Applied mathematics.
Engineering mathematics.
Electronic resources (E-books)
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.
Table of Contents:
  • 1. Integrated Floorplanning and Interconnect Planning
  • 2. Interconnect Planning
  • 3. Modern Standard-cell Placement Techniques
  • 4. Non-Hanan Optimization for Global VLSI Interconnect
  • 5. Techniques for Timing-Driven Routing
  • 6. Interconnect Modeling and Design with Consideration of Inductance
  • 7. Modeling and Characterization of IC Interconnects and Packagings for the Signal Intergrity Verification on High-Performance VLSI Circuits
  • 8. Tradeoffs in Digital Binary Adder Design: the Effects of Floorplanning, Number of Levels of Metals, and Supply Voltage on Performance and Area.

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