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|a Power-Aware Computer Systems
|h [electronic resource] :
|b First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers /
|c edited by B. Falsafi, T.N. Vijaykumar.
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| 250 |
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|a 1st ed. 2001.
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| 264 |
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|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2001.
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| 300 |
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|a X, 158 p.
|b online resource.
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|a Lecture Notes in Computer Science,
|x 0302-9743 ;
|v 2008
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| 490 |
1 |
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|a Springer eBook Collection
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| 505 |
0 |
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|a Power-Aware Microarchitectural/Circuit Techniques -- System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors -- Ramp Up/Down Functional Unit to Reduce Step Power -- An Adaptive Issue Queue for Reduced Power at High Performance -- Application/Compiler Optimizations -- Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform -- Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering -- Compiler-Directed Dynamic Frequency and Voltage Scheduling -- Exploiting IPC/Memory Slack -- Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power -- Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors -- Power/Performance Models and Tools -- TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator -- Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor -- A Comparison of Two Architectural Power Models.
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|a The phenomenal increases in computer system performance in recent years have been accompanied by a commensurate increase in power and energy dissipation. The latter has directly resulted in demand for expensive packaging and cooling technology, an increase in product cost, and a decrease in product reliability in all segments of the computing market. Moreover, the higher power/energy dissipation has signi cantly reduced battery life in portable systems. While - stem designers have traditionally relied on circuit-level techniques to reduce - wer/energy, there is a growing need to address power/energy dissipation at all levels of the computer system. We are pleased to welcome you to the proceedings of the Power-Aware C- puter Systems (PACS 2000) workshop. PACS 2000 was the rst workshop in its series and its aim was to bring together experts from academia and industry to address power-/energy-awareness at all levels of computer systems. In these p- ceedings, we bring you several excellent research contributions spanning a wide spectrum of areas in power-aware systems, from application all the way to c- pilers and microarchitecture, and to power/performance estimating models and tools. We have grouped the contributions into the following speci c categories: (1) power-aware microarchitectural/circuit techniques, (2) application/compiler power optimizations, (3) exploiting opportunity for power optimization in - struction scheduling and cache memories, and (4) power/performance models and tools.
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|a Loaded electronically.
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|a Electronic access restricted to members of the Holy Cross Community.
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|a Electronics.
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|a Microelectronics.
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| 650 |
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|a Architecture, Computer.
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| 650 |
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|a Computer organization.
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| 650 |
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|a Computer hardware.
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| 650 |
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|a Computer programming.
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| 650 |
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|a Programming languages (Electronic computers).
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| 690 |
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|a Electronic resources (E-books)
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1 |
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|a Falsafi, B.
|e editor.
|4 edt
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| 700 |
1 |
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|a Vijaykumar, T.N.
|e editor.
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|x 0302-9743 ;
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