Power-Aware Computer Systems First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers / edited by B. Falsafi, T.N. Vijaykumar.

The phenomenal increases in computer system performance in recent years have been accompanied by a commensurate increase in power and energy dissipation. The latter has directly resulted in demand for expensive packaging and cooling technology, an increase in product cost, and a decrease in product...

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Bibliographic Details
Corporate Author: SpringerLink (Online service)
Other Authors: Falsafi, B. (Editor), Vijaykumar, T.N (Editor)
Format: eBook
Language:English
Published: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2001.
Edition:1st ed. 2001.
Series:Lecture Notes in Computer Science, 2008
Springer eBook Collection.
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Online Access:Click to view e-book
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Table of Contents:
  • Power-Aware Microarchitectural/Circuit Techniques
  • System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors
  • Ramp Up/Down Functional Unit to Reduce Step Power
  • An Adaptive Issue Queue for Reduced Power at High Performance
  • Application/Compiler Optimizations
  • Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform
  • Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering
  • Compiler-Directed Dynamic Frequency and Voltage Scheduling
  • Exploiting IPC/Memory Slack
  • Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
  • Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors
  • Power/Performance Models and Tools
  • TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator
  • Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor
  • A Comparison of Two Architectural Power Models.