Power Distribution Networks in High Speed Integrated Circuits

Power Distribution Networks in High Speed Integrated Circuits by Andrey Mezhiba, Eby G. Friedman.

Distributing power in high speed, high complexity integrated circuits has become a challenging task as power levels exceeding tens of watts have become commonplace while the power supply is plunging toward one volt. This book is dedicated to this important subject. The primary purpose of this monogr...

Full description

Saved in:
Bibliographic Details
Main Authors: Mezhiba, Andrey (Author), Friedman, Eby G. (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 2004.
Edition:1st ed. 2004.
Series:Springer eBook Collection.
Subjects:
Electronic circuits.
Electrical engineering.
Electronic resources (E-books)
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.
Table of Contents:
  • 1. Introduction
  • 1.1 Evolution of integrated circuit technology
  • 1.2 Evolution of design objectives
  • 1.3 The problem of power distribution
  • 1.4 Deleterious effects of power distribution noise
  • 1.5 Book outline
  • 2. Inductive Properties of Electric Circuits
  • 2.1 Definitions of inductance
  • 2.2 Variation of inductance with frequency
  • 2.3 Inductive behavior of circuits
  • 2.4 Inductive properties of on-chip interconnect
  • 2.5 Summary
  • 3. Properties of On-Chip Inductive Current Loops
  • 3.1 Introduction
  • 3.2 Dependence of inductance on line length
  • 3.3 Inductive coupling between two parallel loop segments
  • 3.4 Application to circuit analysis
  • 3.5 Summary
  • 4. Electromigration
  • 4.1 Physical mechanism of electromigration
  • 4.2 Electromigration-induced mechanical stress
  • 4.3 Steady state limit of electromigration damage
  • 4.4 Dependence of electromigration lifetime on the line dimensions
  • 4.5 Statistical distribution of electromigration lifetime
  • 4.6 Electromigration lifetime under AC current
  • 4.7 Electromigration in novel interconnect technologies
  • 4.8 Designing for electromigration reliability
  • 4.9 Summary
  • 5. High Performance Power Distribution Systems
  • 5.1 Physical structure of a power distribution system
  • 5.2 Circuit model of a power distribution system
  • 5.3 Output impedance of a power distribution system
  • 5.4 A power distribution system with a decoupling capacitor
  • 5.5 Hierarchical placement of decoupling capacitance
  • 5.6 Resonance in power distribution networks
  • 5.7 Full impedance compensation
  • 5.8 Case study
  • 5.9 Design considerations
  • 5.10 Limitations of the one-dimensional circuit model
  • 5.11 Summary
  • 6. On-Chip Power Distribution Networks
  • 6.1 Styles of on-chip power distribution networks
  • 6.2 Allocation of on-chip decoupling capacitance
  • 6.3 Die-package interface
  • 6.4 Other considerations
  • 6.5 Summary
  • 7. Computer-Aided Design and Analysis
  • 7.1 Design flow for on-chip power distribution networks
  • 7.2 Linear analysis of power distribution networks
  • 7.3 Modeling power distribution networks
  • 7.4 Characterizing the power current requirements of on-chip circuits
  • 7.5 Numerical methods for analyzing power distribution networks
  • 7.6 Summary
  • 8. Inductive Properties of On-Chip Power Distribution Grids
  • 8.1 Power transmission circuit
  • 8.2 Simulation setup
  • 8.3 Grid types
  • 8.4 Inductance versus line width
  • 8.5 Dependence of inductance on grid type
  • 8.6 Dependence of Inductance on grid dimensions
  • 8.7 Summary
  • 9. Variation of Grid Inductance with Frequency
  • 9.1 Analysis approach
  • 9.2 Discussion of inductance variation
  • 9.3 Summary
  • 10. Inductance/Area/Resistance Tradeoffs
  • 10.1 Inductance vs. resistance tradeoff under a constant grid area constraint
  • 10.2 Inductance vs. area tradeoff under a constant grid resistance constraint
  • 10.3 Summary
  • 11. Scaling Trends Of On-Chip Power Distribution Noise
  • 11.1 Prior work
  • 11.2 Interconnect characteristics
  • 11.3 Model of power supply noise
  • 11.4 Power supply noise scaling
  • 11.5 Implications of noise scaling
  • 11.6 Summary
  • 12. Impedance Characteristics of Multi-Layer Grids
  • 12.1 Electrical properties of multi-layer grids
  • 12.2 Case study of a two layer grid
  • 12.3 Design implications
  • 12.4 Summary
  • 13. Inductive Effects In On-Chip Power Distribution Networks
  • 13.1 Scaling effects in chip-package resonance
  • 13.2 Propagation of power distribution noise
  • 13.3 Local inductive behavior
  • 13.4 Summary
  • 14. Conclusions
  • References
  • About the Authors.

Similar Items