VHDL Answers to Frequently Asked Questions

VHDL Answers to Frequently Asked Questions by Ben Cohen.

VHDL Answers to Frequently asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp. lang. vhdl newsgroup. During his experiences, he w...

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Bibliographic Details
Main Author: Cohen, Ben (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 1998.
Edition:2nd ed. 1998.
Series:Springer eBook Collection.
Subjects:
Electronic circuits.
Computer hardware.
Electrical engineering.
Computer-aided engineering.
Electronic resources (E-books)
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.
Table of Contents:
  • 1. Language Elements
  • 1.1 Why VHDL for Digital Designs
  • 1.2 Salient Points of Concurrent Statements
  • 1.3 Guarded Signal Assignments
  • 1.4 Signals and Ports
  • 1.5 Configurations
  • 1.6 Arithmetic Issues and Operators
  • 1.7 PACKAGE STD_LOGIC_1164
  • 1.8 Range Constraint in Type Definition
  • 1.9 Shared Variables
  • 2. Arrays
  • 2.1 Array Structure Representations
  • 2.2 Arrays — Legal Operations
  • 2.3 Array Slices and Ranges
  • 2.4 Array Initialization
  • 2.5 Constant Arrays in Case
  • 2.6 Constrained and Unconstrained Arrays
  • 2.7 Mapping Arrays of Different Sizes
  • 2.8 Unconstrained Aggregate with “Others ”
  • 2.9 Illegal Array Types
  • 3. Drivers
  • 3.1 Multiple Drivers — Case 1
  • 3.2 Multiple Drivers — Case 2
  • 3.3 Multiple Drivers Error — Case 3
  • 3.4 Multiple Drivers Error — Component
  • 3.5 Coding Style for Detection of Multiple Drivers
  • 4. Subprograms
  • 4.1 Side Effects From A Procedure
  • 4.2 Garbage Collection of Dynamically Created Objects
  • 4.3 Acceptable Types in Parameter Lists for Function Calls
  • 4.4 Files Declarations in Procedures
  • 4.5 Multiple Accesses of Same File
  • 4.6 File Array
  • 4.7 Conversion Function From Integer To Time
  • 4.8 Normalization In Subprograms
  • 5. Packages
  • 5.1 Converting Typed Objects To Strings
  • 5.2 Printing Objects From Vhdl
  • 5.3 Multiple Input Signature Register (Misr)
  • 5.4 Design of a Linear Feedback Shift Register (Lfsr)
  • 5.5 Random Number Generation
  • 5.6 Deferred Constant in Package Declaration
  • 5.7 Complex Numbers and Overloaded Operators
  • 5.8 Ieee Standards
  • 6. Models
  • 6.1 Large Ram Model For Simulation.
  • 6.2 Zero Ohm Resistor (Wire, Bridge) Model
  • 6.3 Error Injector Model
  • 6.4 Transfer Gate (Switch)
  • 7. Synthesis
  • 7.1 Supported/Unsupported Constructs for Synthesis
  • 7.2 Synthesis Sensitivity Rules
  • 7.3 Latch/Register/Combinational Logic
  • 7.4 Latch Inferrance in Functions
  • 7.5 Variable Initialization and Lifetime
  • 7.6 Wait Statement
  • 7.7 Defining Shift Registers in Synthesis
  • 7.8 Register File
  • 7.9 Multiplexer Model
  • 7.10 Demultiplexer Model
  • 7.11 Barrel Shifter
  • 7.12 Use of “don’t Care” in Case Statement
  • 7.13 Parameterized Priority Encoder
  • 7.14 Generating A Synchronous Precharge
  • 7.15 Technology and Vhdl Code Design
  • 7.16 Synthesizing Tri-States
  • 7.17 Subelement Association
  • 7.18 Finite State Machine (Fsm)
  • 7.19 One-Hot Encoding
  • 7.20 Instantiating Synopsys® Designware Components
  • 7.21 Resource Sharing
  • 7.22 Applying Digital Design Experiences
  • 7.23 Address Range Identification Via Inferred Comparator
  • 7.24 Port Mapping to Ground Or Vcc
  • 7.25 Bit Reversal
  • 7.26 How to Design a Timer in Vhdl
  • 7.27 Specifying a Multiplier
  • 7.28 Behavioral Synthesis
  • 8. Design Verification and Testbench
  • 8.1 Verification Processes
  • 8.2 Functional Verification
  • 8.3 Regression Tests
  • 8.4 Formal Verification
  • 8.5 Bus Functional Model (Bfm) Modeling
  • 8.6 Application of Misr, Random, Lfsr Packages for Auto-Regression
  • 8.7 Strength Stripper
  • 9. Potpourri
  • 9.1 Methods To Enhance Simulation Speed
  • 9.2 Accessing Signals Internal to Components
  • 9.3 Transferring a Line Onto a Signal
  • 9.4 Type Declaration in Multiple Packages
  • 9.5 Internet - Frequently Asked Questions
  • 9.6 Vhdl Text Editor?
  • 9.7 Vital
  • 9.8 Behavioral Modeling
  • 9.9 Final Vhdl Exam
  • 10. Design for Reuse
  • 10.1 Design Processes for Reusability
  • 10.2 Parameterized, Reusable and Readable Code
  • 10.3 Documentation of Vhdl Designs
  • Appendix A: Vhdl’93 and Vhdl’87 Syntax Summary
  • Appendix B: Package Standard
  • Appendix C: Package Textio
  • Appendix D: Package Std_Logic_1164
  • Appendix E: Package Std_Logic_Arith
  • Appendix F: Vhdl Predefined Attributes.

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