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|a 9781402080241
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|a 10.1007/b117092
|2 doi
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|a Iman, Sasan.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
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|a The e Hardware Verification Language
|h [electronic resource] /
|c by Sasan Iman, Sunita Joshi.
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| 250 |
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|a 1st ed. 2004.
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| 264 |
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|a New York, NY :
|b Springer US :
|b Imprint: Springer,
|c 2004.
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|a XXII, 349 p.
|b online resource.
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|a text
|b txt
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|a Springer eBook Collection
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|a Verification Methodologies and Environment Architecture -- Verification Methodologies -- Anatomy of a Verification Environment -- All About e -- e as a Programming Language -- e as a Verification Language -- Topology and Stimulus Generation -- Generator Operation -- Data Modeling and Stimulus Generation -- Sequence Generation -- Response Collection, Data Checking, and Property Monitoring -- Temporal Expressions -- Messages -- Collectors and Monitors -- Scoreboarding -- Coverage Modeling and Measurement -- Coverage Engine -- Coverage Modeling -- e Code Reuse -- e Reuse Methodology -- si_util Package.
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| 520 |
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|a I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed.
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|a Loaded electronically.
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|a Electronic access restricted to members of the Holy Cross Community.
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|a Computers.
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|a Electronic circuits.
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|a Electrical engineering.
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|a Computer-aided engineering.
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| 690 |
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|a Electronic resources (E-books)
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| 700 |
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|a Joshi, Sunita.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
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| 710 |
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|a SpringerLink (Online service)
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|t Springer eBooks
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|u https://holycross.idm.oclc.org/login?auth=cas&url=https://doi.org/10.1007/b117092
|3 Click to view e-book
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