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|a Kesidis, George.
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|a ATM Network Performance
|h [electronic resource] /
|c by George Kesidis.
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|a 2nd ed. 2000.
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|a New York, NY :
|b Springer US :
|b Imprint: Springer,
|c 2000.
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|a XIV, 206 p.
|b online resource.
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|a The Springer International Series in Engineering and Computer Science,
|x 0893-3405 ;
|v 537
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|a Springer eBook Collection
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|a 1 Introduction -- 1.1 ATM Background -- 1.2 A Queueing Model of an ATM Network -- 1.3 The Evolving Internet -- 1.4 Organization of the Book -- 1.5 Discussion and Additional References -- 2 Discrete-Time Queues with Constant Service Rate -- 2.1 Discrete-Time Lindley Processes -- 2.2 (?, p) Constraints -- 2.3 Obtaining (?, p) Constraints via Leaky Buckets -- 2.4 Large Deviations Effective Bandwidths -- 2.5 Extremal (?, p) and Peak-Rate Constrained Traffic -- 2.6 Discussion and Additional References -- 2.7 Exercises -- 3 Bandwidth Scheduling for a Single Node -- 3.1 The Guaranteed-Rate Property -- 3.2 Round-Robin Schedulers -- 3.3 Schedulers Based on Virtual Finishing Times -- 3.4 Fair Scheduling -- 3.5 General Design Issues of Bandwidth Schedulers -- 3.6 Discussion and Additional References -- 3.7 Exercises -- 4 End-To-End Delay Bounds and Buffer Sizing -- 4.1 End-to-End Delay Bounds -- 4.2 Buffer Sizing for Lossless Transmission -- 4.3 Buffer Sizing For Idling Schedulers -- 4.4 Controlling Cell Delay Jitter -- 4.5 Extensions to Arbitrary Virtual Path Connections -- 4.6 Discussion and Additional References -- 4.7 Exercises -- 5 The Flow Control Problem for ABR Traffic -- 5.1 ABR Parameters -- 5.2 Resource Management Cells -- 5.3 RM Cell Delays -- 5.4 Buffer Sizing -- 5.5 Excess Bandwidth -- 5.6 Distributing Excess Bandwidth Fairly -- 5.7 Evaluating a Flow Control Policy -- 5.8 Discussion and References -- 6 ATM Switches with the Guaranteed-Rate Property -- 6.1 Single-Stage Switches -- 6.2 General Design Issues for Single-Stage Switches -- 6.3 Output-Buffered ATM Switches -- 6.4 Input-Buffered ATM Switches -- 6.5 Scalability -- 6.6 Input/Output-Buffering -- 6.7 Multicast Scheduling for Input-Buffered Switches -- 6.8 Discussion and Additional References -- 6.9 Exercises -- 7 Resource Provisioning for Prerecorded Video -- 7.1 Piecewise-CBR Service -- 7.2 Quality-of-Service Requirements -- 7.3 End-to-End Provisioning -- 7.4 Discussion and Additional References -- 7.5 Exercises -- 8 Real-Time VBR Video Teleconferencing -- 8.1 A VPC for a Real-Time Video Bundle -- 8.2 QoS Requirements of the Video Flow -- 8.3 Bandwidth Requirements at Each Hop -- 8.4 Admission Control Summary -- 8.5 On-Line Traffic Measurements -- 8.6 Discussion and Additional References -- 8.7 Exercises -- References -- A Glossary of Acronyms and Short Forms -- B Solutions and References for Selected Exercises.
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| 520 |
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|a ATM Network Performance, Second Edition, describes approaches to computer and communication network management at the ATM layer of the protocol hierarchy. The focus is on satisfying quality-of-service requirements for individual connections. Results in both areas of bandwidth scheduling and traffic control are explained. Recent results in end-to-end performance, provisioning for video connections and statistical multiplexing are also described. All of the material has been updated where appropriate and new references added and expanded. Timely updates: Entirely new chapter on ATM switches with an emphasis on scalable-to-terabit switching. New material on round-robin scheduling, jitter control, QoS paradigms as well as special treatment of fluid modeling and variable bit rate channel capacity. Expanded coverage of CBR channels, IP over ATM, and guaranteed-rate performance. Substantial increase in end-of-chapter exercises. Solutions for selected exercises in separate appendix. Complete solutions for all exercises also available from author.
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|a Electronic access restricted to members of the Holy Cross Community.
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