Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method

Hierarchical Annotated Action Diagrams An Interface-Oriented Specification and Verification Method / by Eduard Cerny, Bachir Berkane, Pierre Girodias, Karim Khordoc.

Standardization of hardware description languages and the availability of synthesis tools has brought about a remarkable increase in the productivity of hardware designers. Yet design verification methods and tools lag behind and have difficulty in dealing with the increasing design complexity. This...

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Bibliographic Details
Main Authors: Cerny, Eduard (Author), Berkane, Bachir (Author), Girodias, Pierre (Author), Khordoc, Karim (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 1998.
Edition:1st ed. 1998.
Series:Springer eBook Collection.
Subjects:
Electronic circuits.
Artificial intelligence.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic resources (E-books)
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.
Table of Contents:
  • 1 Introduction
  • 1.1 Digital System Design and Verification
  • 1.2 Interface-Oriented Models
  • 1.3 Purpose and Organization of the Book
  • 2 Overview of HAAD Method
  • 2.1 Leaf Action Diagrams
  • 2.2 Annotations in Leaf Action Diagrams
  • 2.3 Hierarchical Action Diagrams
  • 2.4 Annotations in HAAD Hierarchy
  • 3 Formal Characterization of HAAD
  • 3.1 Leaf-Level Action Diagram Algebra
  • 3.2 Verification
  • 3.3 Language of Hierarchical Action Diagrams
  • 3.4 Related work
  • 4 HAAD VHDL Model
  • 4.1 Execution of HAAD VHDL Models
  • 4.2 Execution of Hierarchical Action Diagrams
  • 4.3 Occurrence Time Enumeration of Output Actions
  • 4.4 Enumeration and Delay Correlation
  • 4.5 Organization of a HAAD Model in VHDL
  • 5 Consistency, Causality and Compatibility
  • 5.1 Introduction
  • 5.2 Basic Concepts
  • 5.3 Problems
  • 5.4 BlockMachines
  • 5.5 Derived Block Machines
  • 5.6 Causal Action Diagrams
  • 5.7 Compatibility of Action Diagrams
  • 5.8 Conclusions
  • 6 Interface Verification using CLP
  • 6.1 Interface Timing Verification
  • 6.2 Constraint Logic Programming
  • 6.3 The Event Separation Problem
  • 6.4 Delay Correlation
  • 6.5 CSP and CLP Based on RIA
  • 6.6 Solving ITV with CLP Based on RIA
  • 6.7 Examples
  • 6.8 Experimental Results
  • 6.9 Concluding Remarks
  • 7 Example: Interfacing ARM7 and a Static RAM
  • 7.1 Problem Definition
  • 7.2 Bus Functional Model of ARM7 Subset
  • 7.3 Bus Functional Model of RAM
  • 7.4 VHDL Model of interface transducer
  • 7.5 Putting it all together
  • 7.6 Static Interface Timing Verification
  • 8 Summary and Recent Developments
  • 8.1 Summary
  • 8.2 Recent Developments
  • 8.3 Future Directions
  • References
  • A Grammar of the HAAD Language
  • A.1 Conventions
  • A.2 Semantic Notes
  • A.2.1 Generics
  • A.2.2 Name Spaces
  • A.2.3 Default Constraint Bounds
  • A.3 Grammar Definition
  • B Proofs for Chapter
  • B.1 Proof of Theorem 3.1
  • B.2 Proof of Theorem 3.2, 3.3, 3.4, and 3.5
  • B.3 Proof of Theorem 3.6
  • B.4 Proof of Theorem 3.7
  • B.5 Proof of Theorem 8
  • B.6 Proof of Theorem 3.9
  • B.7 Proof of Theorem 3.10.

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