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|a 9783540693390
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7 |
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|a 10.1007/BFb0028725
|2 doi
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|a (DE-He213)978-3-540-69339-0
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1 |
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|a Computer Aided Verification
|h [electronic resource] :
|b 10th International Conference, CAV'98, Vancouver, BC, Canada, June 28-July 2, 1998, Proceedings /
|c edited by Alan J. Hu, Moshe Y. Vardi.
|
| 250 |
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|a 1st ed. 1998.
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| 264 |
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1 |
|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 1998.
|
| 300 |
|
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|a X, 552 p.
|b online resource.
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| 336 |
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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| 338 |
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|a online resource
|b cr
|2 rdacarrier
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| 347 |
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|a text file
|b PDF
|2 rda
|
| 490 |
1 |
|
|a Lecture Notes in Computer Science,
|x 0302-9743 ;
|v 1427
|
| 490 |
1 |
|
|a Springer eBook Collection
|
| 505 |
0 |
|
|a Synchronous programming of reactive systems -- Ten years of partial order reduction -- An ACL2 proof of write invalidate cache coherence -- Transforming the theorem prover into a digital design tool: From concept car to off-road vehicle -- A role for theorem proving in multi-processor design -- A formal method experience at secure computing corporation -- Formal methods in an industrial environment -- On checking model checkers -- Finite-state analysis of security protocols -- Integrating proof-based and model-checking techniques for the formal verification of cryptographic protocols -- Verifying systems with infinite but regular state spaces -- Formal verification of out-of-order execution using incremental flushing -- Verification of an implementation of Tomasulo's algorithm by compositional model checking -- Decomposing the proof of correctness of pipelined microprocessors -- Processor verification with precise exceptions and speculative execution -- Symmetry reductions in model checking -- Structural symmetry and model checking -- Using magnetic disk instead of main memory in the Mur ? verifier -- On-the-fly model checking of RCTL formulas -- From pre-historic to post-modern symbolic model checking -- Model checking LTL using net unforldings -- Model checking for a first-order temporal logic using multiway decision graphs -- On the limitations of ordered representations of functions -- BDD based procedures for a theory of equality with uninterpreted functions -- Computing reachable control states of systems modeled with uninterpreted functions and infinite memory -- Multiple counters automata, safety analysis and presburger arithmetic -- A comparison of Presburger engines for EFSM reachability -- Generating finite-state abstractions of reactive systems using decision procedures -- On-the-fly analysis of systems with unbounded, lossy FIFO channels -- Computing abstractions of infinite state systems compositionally and automatically -- Normed simulations -- An experiment in parallelizing an application using formal methods -- Efficient symbolic detection of global properties in distributed systems -- A machine-checked proof of the optimality of a real-time scheduling policy -- A general approach to partial order reductions in symbolic verification -- Correctness of the concurrent approach to symbolic verification of interleaved models -- Verification of timed systems using POSETs -- Mechanising BAN Kerberos by the inductive method -- Protocol verification in Nuprl -- You assume, we guarantee: Methodology and case studies -- Verification of a parameterized bus arbitration protocol -- The ‘test model-checking’ approach to the verification of formal memory models of multiprocessors -- Design constraints in symbolic model checking -- Verification of floating-point adders -- Xeve, an Esterel verification environment -- InVeSt : A tool for the verification of invariants -- Verifying mobile processes in the HAL environment -- MONA 1.x: New techniques for WS1S and WS2S -- MOCHA: Modularity in model checking -- SCR: A toolset for specifying and analyzing software requirements -- A toolset for message sequence charts -- Real-time verification of Statemate designs -- Optikron: A tool suite for enhancing model-checking of real-time systems -- Kronos: A model-checking tool for real-time systems.
|
| 520 |
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|a This book consitutes the refereed proceedings of the 10th International Conference on Computer Aided Verification, CAV'98, held in Vancouver, BC, Canada, in June/July 1998. The 33 revised full papers and 10 tool papers presented were carefully selected from a total of 117 submissions. Also included are 11 invited contributions. Among the topics covered are modeling and specification formalisms; verification techniques like state-space exploration, model checking, synthesis, and automated deduction; various verification techniques; applications and case studies, and verification in practice.
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| 590 |
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|a Loaded electronically.
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| 590 |
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|a Electronic access restricted to members of the Holy Cross Community.
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| 650 |
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0 |
|a Software engineering.
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| 650 |
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0 |
|a Computers.
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| 650 |
|
0 |
|a Computer logic.
|
| 650 |
|
0 |
|a Mathematical logic.
|
| 650 |
|
0 |
|a Logic design.
|
| 690 |
|
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|a Electronic resources (E-books)
|
| 700 |
1 |
|
|a Hu, Alan J.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Vardi, Moshe Y.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 710 |
2 |
|
|a SpringerLink (Online service)
|
| 773 |
0 |
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|t Springer eBooks
|
| 830 |
|
0 |
|a Lecture Notes in Computer Science,
|x 0302-9743 ;
|v 1427
|
| 830 |
|
0 |
|a Springer eBook Collection.
|
| 856 |
4 |
0 |
|u https://holycross.idm.oclc.org/login?auth=cas&url=https://doi.org/10.1007/BFb0028725
|3 Click to view e-book
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