SystemVerilog For Design A Guide to Using SystemVerilog for Hardware Design and Modeling / by Stuart Sutherland, Simon Davidmann, Peter Flake.

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Bibliographic Details
Main Authors: Sutherland, Stuart (Author), Davidmann, Simon (Author), Flake, Peter (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 2004.
Edition:1st ed. 2004.
Series:Springer eBook Collection.
Subjects:
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.

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505 0 |a 1: Introduction to SystemVerilog -- 2: SystemVerilog Literal Values and Built-in Data Types -- 3: SystemVerilog User-Defined and Enumerated Data Types -- 4: SystemVerilog Arrays, Structures and Unions -- 5: SystemVerilog Procedural Blocks, Tasks and Functions -- 6: SystemVerilog Procedural Statements -- 7: Modeling Finite State Machines with SystemVerilog -- 8: SystemVerilog Design Hierarchy -- 9: SystemVerilog Interfaces -- 10: A Complete Design Modeled with SystemVerilog -- 11: Behavioral and Transaction Level Modeling -- Appendix A: The SystemVerilog Formal Definition (BNF) -- Appendix B: A History of SUPERLOG, The Beginning of SystemVerilog. 
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