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00000nam a22000005i 4500 |
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b3224027 |
| 003 |
MWH |
| 005 |
20191024001318.0 |
| 007 |
cr nn 008mamaa |
| 008 |
121227s2001 xxu| s |||| 0|eng d |
| 020 |
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|a 9781461514770
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| 024 |
7 |
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|a 10.1007/978-1-4615-1477-0
|2 doi
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| 035 |
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|a (DE-He213)978-1-4615-1477-0
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| 050 |
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4 |
|a E-Book
|
| 072 |
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7 |
|a TJFC
|2 bicssc
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| 072 |
|
7 |
|a TEC008010
|2 bisacsh
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| 072 |
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7 |
|a TJFC
|2 thema
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| 100 |
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|a Brayton, Robert K.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
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| 245 |
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|a Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics
|h [electronic resource] /
|c by Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli.
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| 250 |
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|a 1st ed. 2001.
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| 264 |
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|a New York, NY :
|b Springer US :
|b Imprint: Springer,
|c 2001.
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| 300 |
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|a XIX, 112 p.
|b online resource.
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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| 338 |
|
|
|a online resource
|b cr
|2 rdacarrier
|
| 347 |
|
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|a text file
|b PDF
|2 rda
|
| 490 |
1 |
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|a Springer eBook Collection
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| 505 |
0 |
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|a 1. Introduction -- 1.1 Cross-talk in DSM IC Design -- 1.2 Book Overview -- 1.3 Book Outline -- 2. Validating Deep Sub-Micron Effects -- 2.1 Chapter Overview -- 2.2 Trends in DSM VLSI Interconnect -- 2.3 Predicting VLSI Process Technology Trends -- 2.4 Extracting On-chip Layout Parasitics -- 2.5 Validating Cross-talk Effects -- 2.6 Review of Existing Techniques -- 2.7 Chapter Summary -- 3. VLSI Layout Fabrics -- 3.1 Chapter Overview -- 3.2 Our Dense Wiring Fabric (DWF) -- 3.3 Advantages -- 3.4 Disadvantages -- 3.5 Chapter Summary -- 4. Fabric1 - Fabric Cell Based Design -- 4.1 Chapter Overview -- 4.2 Design Flow 1 -- 4.3 Design Flow 2 -- 4.4 Chapter Summary -- 5. Fabric3 - Network of PLA Based Design -- 5.1 Chapter Overview -- 5.2 Programmable Logic Arrays -- 5.3 Networks of Programmable Logic Arrays -- 5.4 Synthesis Algorithms for the Network of PLAs Methodology -- 5.5 Design Flow 1 -- 5.6 Design Flow 2 -- 5.7 Discussion -- 5.8 Chapter Summary -- 6. Wire Removal in a Network of PLAS -- 6.1 Chapter Overview -- 6.2 Binary SPFDs -- 6.3 MV-SPFDs -- 6.4 Experimental Results -- 6.5 Chapter Summary -- 7. Conclusions and Future Directions -- 7.1 Conclusions -- 7.2 Future Work -- Appendices -- Standard Cells.
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| 520 |
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|a This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems like cross-talk, electromigration, self-heat, etc. are becoming important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wires. Typical approaches to tackle the cross-talk problem attempt to fix the problem once it is created. In our approach, we ensure that cross-talk is eliminated by design. The work described in this book attempts to take an "outside-the-box" view and propose a radically different design style. This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes. With our choice of fabric, cross-talk between adjacent wires on an IC is reduced by between one and two orders of magnitude. In this way, the fabric concept eliminates cross-talk up-front, and by design. We propose two separate design flows, each of which uses the fabric concept to implement logic. The first flow uses fabric-compliant standard cells as an im plementation vehicle. We call these cells fabric cells, and they have the same logic functionality as existing standard cells with which they are compared.
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| 590 |
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|a Loaded electronically.
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| 590 |
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|a Electronic access restricted to members of the Holy Cross Community.
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| 650 |
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|a Electronic circuits.
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| 650 |
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|a Electrical engineering.
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| 650 |
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|a Computer-aided engineering.
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| 690 |
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|a Electronic resources (E-books)
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| 700 |
1 |
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|a Sangiovanni-Vincentelli, Alberto L.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
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| 710 |
2 |
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|a SpringerLink (Online service)
|
| 773 |
0 |
|
|t Springer eBooks
|
| 830 |
|
0 |
|a Springer eBook Collection.
|
| 856 |
4 |
0 |
|u https://holycross.idm.oclc.org/login?auth=cas&url=https://doi.org/10.1007/978-1-4615-1477-0
|3 Click to view e-book
|
| 907 |
|
|
|a .b32240272
|b 04-18-22
|c 02-26-20
|
| 998 |
|
|
|a he
|b 02-26-20
|c m
|d @
|e -
|f eng
|g xxu
|h 0
|i 1
|
| 912 |
|
|
|a ZDB-2-ENG
|
| 912 |
|
|
|a ZDB-2-BAE
|
| 950 |
|
|
|a Engineering (Springer-11647)
|
| 902 |
|
|
|a springer purchased ebooks
|
| 903 |
|
|
|a SEB-COLL
|
| 945 |
|
|
|f - -
|g 1
|h 0
|j - -
|k - -
|l he
|o -
|p $0.00
|q -
|r -
|s b
|t 38
|u 0
|v 0
|w 0
|x 0
|y .i21371921
|z 02-26-20
|
| 999 |
f |
f |
|i 8d468420-10bd-59d3-af7e-609ca383f806
|s 95344ead-d137-5d46-94b7-f431816c591a
|
| 952 |
f |
f |
|p Online
|a College of the Holy Cross
|b Main Campus
|c E-Resources
|d Online
|e E-Book
|h Library of Congress classification
|i Elec File
|n 1
|