Algorithms for Synthesis and Testing of Asynchronous Circuits

Algorithms for Synthesis and Testing of Asynchronous Circuits by Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli.

Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by the progressive shift towards synchronous design techniques that had much more structur...

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Bibliographic Details
Main Authors: Lavagno, Luciano (Author), Sangiovanni-Vincentelli, Alberto L. (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 1993.
Edition:1st ed. 1993.
Series:The Springer International Series in Engineering and Computer Science, 232
Springer eBook Collection.
Subjects:
Electronic circuits.
Electrical engineering.
Computer-aided engineering.
Electronic resources (E-books)
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.
Table of Contents:
  • 1 Introduction
  • 1.1 Motivation
  • 1.2 Organization
  • 2 Overview of The Design Methodology
  • 2.1 Signal Transition Graphs
  • 2.2 Signal Transition Graph Synthesis
  • 2.3 The VMEbus Master Interface Protocol
  • 2.4 A Signal Transition Graph Specification for the VMEbus Interface
  • 2.5 The Circuit Implementation of the VMEbus Master Interface
  • 3 Previous Work
  • 3.1 Circuit Model Taxonomy
  • 3.2 Definitions
  • 3.3 The Huffman Model for Asynchronous Circuits
  • 3.4 Micropipelines
  • 3.5 Speed-independent Circuits
  • 3.6 Delay-insensitive Circuits
  • 3.7 Hazard Analysis in Asynchronous Circuits
  • 3.8 Conclusion
  • 4 The Signal Transition Graph Model
  • 4.1 A Low-level Model for Asynchronous Systems
  • 4.2 Modeling Asynchronous Logic Circuits
  • 4.3 A High-level Behavioral Model for Asynchronous Systems
  • 4.4 Classification of Models of Asynchronous Circuits
  • 4.5 Signal Transition Graphs and Change Diagrams
  • 4.6 Conclusion
  • 5 The State Encoding Methodology
  • 5.1 Overview of the State Encoding Methodology
  • 5.2 From Signal Transition Graphs to Finite State Machines
  • 5.3 Constrained Finite State Machine Minimization
  • 5.4 State Signal Insertion
  • 5.5 Experimental Results
  • 6 The Synthesis Methodology
  • 6.1 Hazard Analysis and Signal Transition Graphs
  • 6.2 Circuit Implementation of the Next State Function
  • 6.3 Static Hazard Detection in the Circuit Implementation
  • 6.4 Hazard Elimination by Delay Padding
  • 6.5 Dynamic Hazard Analysis
  • 6.6 Experimental Results
  • 7 The Design For Testability Methodology
  • 7.1 Definitions and Notation
  • 7.2 A Procedure Guaranteed to Generate an HFRPDFT Circuit
  • 7.3 Heuristic Procedures to Improve HFRPDFT Testability
  • 7.4 A Procedure Guaranteed to Generate an RGDFT Circuit
  • 7.5 Design for Delay Testability Methodology
  • 7.6 Experimental Results
  • 8 Conclusions
  • References.

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