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|a 9783540445852
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|a 10.1007/3-540-44585-4
|2 doi
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|a (DE-He213)978-3-540-44585-2
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|a E-Book
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1 |
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|a Computer Aided Verification
|h [electronic resource] :
|b 13th International Conference, CAV 2001, Paris, France, July 18-22, 2001. Proceedings /
|c edited by Gerard Berry, Hubert Comon, Alain Finkel.
|
| 250 |
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|a 1st ed. 2001.
|
| 264 |
|
1 |
|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2001.
|
| 300 |
|
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|a XIII, 522 p.
|b online resource.
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| 336 |
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|a text
|b txt
|2 rdacontent
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|a online resource
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| 347 |
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|a text file
|b PDF
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|
| 490 |
1 |
|
|a Lecture Notes in Computer Science,
|x 0302-9743 ;
|v 2102
|
| 490 |
1 |
|
|a Springer eBook Collection
|
| 505 |
0 |
|
|a Invited Talk -- Software Documentation and the Verification Process -- Model Checking and Theorem Proving -- Certifying Model Checkers -- Formalizing a JVML Verifier for Initialization in a Theorem Prover -- Automated Inductive Verification of Parameterized Protocols? -- Automata Techniques -- Efficient Model Checking Via Büchi Tableau Automata? -- Fast LTL to Büchi Automata Translation -- A Practical Approach to Coverage in Model Checking -- Verification Core Technology -- A Fast Bisimulation Algorithm -- Symmetry and Reduced Symmetry in Model Checking? -- Transformation-Based Verification Using Generalized Retiming -- BDD and Decision Procedures -- Meta-BDDs: A Decomposed Representation for Layered Symbolic Manipulation of Boolean Functions -- CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination -- Finite Instantiations in Equivalence Logic with Uninterpreted Functions -- Abstraction and Refinement -- Model Checking with Formula-Dependent Abstract Models -- Verifying Network Protocol Implementations by Symbolic Refinement Checking -- Automatic Abstraction for Verification of Timed Circuits and Systems? -- Combinations -- Automated Verification of a Randomized Distributed Consensus Protocol Using Cadence SMV and PRISM? -- Analysis of Recursive State Machines -- Parameterized Verification with Automatically Computed Inductive Assertions? -- Tool Presentations: Rewriting and Theorem-Proving Techniques -- EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations -- AGVI — Automatic Generation, Verification, and Implementation of Security Protocols -- ICS: Integrated Canonizer and Solver? -- µCRL: A Toolset for Analysing Algebraic Specifications -- Truth/SLC — A Parallel Verification Platform for Concurrent Systems -- The SLAM Toolkit -- Invited Talk -- Java Bytecode Verification: An Overview -- Infinite State Systems -- Iterating Transducers -- Attacking Symbolic State Explosion -- A Unifying Model Checking Approach for Safety Properties of Parameterized Systems -- A BDD-Based Model Checker for Recursive Programs -- Temporal Logics and Verification -- Model Checking the World Wide Web? -- Distributed Symbolic Model Checking for ?-Calculus -- Tool Presentations: Model-Checking and Automata Techniques -- The Temporal Logic Sugar -- TReX: A Tool for Reachability Analysis of Complex Systems -- BOOSTER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction -- SDLcheck: A Model Checking Tool -- EASN: Integrating ASN.1 and Model Checking -- Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams -- TAXYS: A Tool for the Development and Verification of Real-Time Embedded Systems? -- Microprocessor Verification, Cache Coherence -- Microarchitecture Verification by Compositional Model Checking -- Rewriting for Symbolic Execution of State Machine Models -- Using Timestamping and History Variables to Verify Sequential Consistency -- SAT, BDDs, and Applications -- Benefits of Bounded Model Checking at an Industrial Setting -- Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers -- Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m) -- Timed Automata -- Job-Shop Scheduling Using Timed Automata? -- As Cheap as Possible: Effcient Cost-Optimal Reachability for Priced Timed Automata -- Binary Reachability Analysis of Pushdown Timed Automata with Dense Clocks.
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| 590 |
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|a Loaded electronically.
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| 590 |
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|a Electronic access restricted to members of the Holy Cross Community.
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| 650 |
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0 |
|a Database management.
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| 650 |
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0 |
|a Computers.
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| 650 |
|
0 |
|a Software engineering.
|
| 650 |
|
0 |
|a Computer logic.
|
| 650 |
|
0 |
|a Mathematical logic.
|
| 650 |
|
0 |
|a Artificial intelligence.
|
| 690 |
|
|
|a Electronic resources (E-books)
|
| 700 |
1 |
|
|a Berry, Gerard.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Comon, Hubert.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 700 |
1 |
|
|a Finkel, Alain.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 710 |
2 |
|
|a SpringerLink (Online service)
|
| 773 |
0 |
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|t Springer eBooks
|
| 830 |
|
0 |
|a Lecture Notes in Computer Science,
|x 0302-9743 ;
|v 2102
|
| 830 |
|
0 |
|a Springer eBook Collection.
|
| 856 |
4 |
0 |
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