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|a 10.1007/11817963
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|a Computer Aided Verification
|h [electronic resource] :
|b 18th International Conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006, Proceedings /
|c edited by Thomas Ball, Robert B. Jones.
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| 250 |
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|a 1st ed. 2006.
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| 264 |
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1 |
|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2006.
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| 300 |
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|a XV, 564 p.
|b online resource.
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| 490 |
1 |
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|a Theoretical Computer Science and General Issues ;
|v 4144
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| 490 |
1 |
|
|a Springer eBook Collection
|
| 505 |
0 |
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|a Invited Talks -- Formal Specifications on Industrial-Strength Code—From Myth to Reality -- I Think I Voted: E-Voting vs. Democracy -- Playing with Verification, Planning and Aspects: Unusual Methods for Running Scenario-Based Programs -- The Ideal of Verified Software -- Session 1. Automata -- Antichains: A New Algorithm for Checking Universality of Finite Automata -- Safraless Compositional Synthesis -- Minimizing Generalized Büchi Automata -- Session 2. Tools Papers -- Ticc: A Tool for Interface Compatibility and Composition -- FAST Extended Release -- Session 3. Arithmetic -- Don’t Care Words with an Application to the Automata-Based Approach for Real Addition -- A Fast Linear-Arithmetic Solver for DPLL(T) -- Session 4. SAT and Bounded Model Checking -- Bounded Model Checking for Weak Alternating Büchi Automata -- Deriving Small Unsatisfiable Cores with Dominators -- Session 5. Abstraction/Refinement -- Lazy Abstraction with Interpolants -- Using Statically Computed Invariants Inside the Predicate Abstraction and Refinement Loop -- Counterexamples with Loops for Predicate Abstraction -- Session 6. Tools Papers -- cascade: C Assertion Checker and Deductive Engine -- Yasm: A Software Model-Checker for Verification and Refutation -- Session 7. Symbolic Trajectory Evaluation -- SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory Evaluation -- Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation -- Session 8. Property Specification and Verification -- Some Complexity Results for SystemVerilog Assertions -- Check It Out: On the Efficient Formal Verification of Live Sequence Charts -- Session 9. Time -- Symmetry Reduction for Probabilistic Model Checking -- Communicating Timed Automata: The More Synchronous, the More Difficult to Verify -- Allen Linear (Interval) Temporal Logic – Translation to LTL and Monitor Synthesis -- Session 10. Tools Papers -- DiVinE – A Tool for Distributed Verification -- EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation -- Session 11. Concurrency -- Symbolic Model Checking of Concurrent Programs Using Partial Orders and On-the-Fly Transactions -- Model Checking Multithreaded Programs with Asynchronous Atomic Methods -- Causal Atomicity -- Session 12. Trees, Pushdown Systems and Boolean Programs -- Languages of Nested Trees -- Improving Pushdown System Model Checking -- Repair of Boolean Programs with an Application to C -- Session 13. Termination -- Termination of Integer Linear Programs -- Automatic Termination Proofs for Programs with Shape-Shifting Heaps -- Termination Analysis with Calling Context Graphs -- Session 14. Tools Papers -- Terminator: Beyond Safety -- CUTE and jCUTE: Concolic Unit Testing and Explicit Path Model-Checking Tools -- Session 15. Abstract Interpretation -- SMT Techniques for Fast Predicate Abstraction -- The Power of Hybrid Acceleration -- Lookahead Widening -- Session 16. Tools Papers -- The Heuristic Theorem Prover: Yet Another SMT Modulo Theorem Prover -- LEVER: A Tool for Learning Based Verification -- Session 17. Memory Consistency -- Formal Verification of a Lazy Concurrent List-Based Set Algorithm -- Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study -- Fast and Generalized Polynomial Time Memory Consistency Verification -- Session 18. Shape Analysis -- Programs with Lists Are Counter Automata -- Lazy Shape Analysis -- Abstraction for Shape Analysis with Fast and Precise Transformers.
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| 590 |
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|a Loaded electronically.
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| 590 |
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|a Electronic access restricted to members of the Holy Cross Community.
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| 650 |
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0 |
|a Computers.
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| 650 |
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0 |
|a Computer logic.
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| 650 |
|
0 |
|a Software engineering.
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| 650 |
|
0 |
|a Mathematical logic.
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| 650 |
|
0 |
|a Artificial intelligence.
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| 650 |
|
0 |
|a Logic design.
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| 690 |
|
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|a Electronic resources (E-books)
|
| 700 |
1 |
|
|a Ball, Thomas.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
|
|a Jones, Robert B.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
|
| 710 |
2 |
|
|a SpringerLink (Online service)
|
| 773 |
0 |
|
|t Springer eBooks
|
| 830 |
|
0 |
|a Theoretical Computer Science and General Issues ;
|v 4144
|
| 830 |
|
0 |
|a Springer eBook Collection.
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| 856 |
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