Low-Power Variation-Tolerant Design in Nanometer Silicon

Low-Power Variation-Tolerant Design in Nanometer Silicon edited by Swarup Bhunia, Saibal Mukhopadhyay.

Low-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-thresh...

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Bibliographic Details
Corporate Author: SpringerLink (Online service)
Other Authors: Bhunia, Swarup (Editor), Mukhopadhyay, Saibal (Editor)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 2011.
Edition:1st ed. 2011.
Series:Springer eBook Collection.
Subjects:
Electronic circuits.
Computer-aided engineering.
Electronic resources (E-books)
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.
Table of Contents:
  • Introduction and Motivation
  • Background on Power Dissipation
  • Background on Parameter Variations
  • Low power Logic Design under Variations
  • Low Power Memory Design under Variations
  • System and Architecture Level Design
  • Emerging Challenges and Solution Approach
  • Conclusion and Discussion.

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