High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings / edited by Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer.

Saved in:
Bibliographic Details
Corporate Author: SpringerLink (Online service)
Other Authors: Stenström, Per (Editor), Dubois, Michel (Editor), Katevenis, Manolis (Editor), Gupta, Rajiv (Editor), Ungerer, Theo (Editor)
Format: eBook
Language:English
Published: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2008.
Edition:1st ed. 2008.
Series:Theoretical Computer Science and General Issues ; 4917
Springer eBook Collection.
Subjects:
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.

MARC

LEADER 00000nam a22000005i 4500
001 b3305411
003 MWH
005 20191025122402.0
007 cr nn 008mamaa
008 100301s2008 gw | s |||| 0|eng d
020 |a 9783540775607 
024 7 |a 10.1007/978-3-540-77560-7  |2 doi 
035 |a (DE-He213)978-3-540-77560-7 
050 4 |a E-Book 
072 7 |a UMB  |2 bicssc 
072 7 |a COM036000  |2 bisacsh 
072 7 |a UMB  |2 thema 
072 7 |a UYF  |2 thema 
245 1 0 |a High Performance Embedded Architectures and Compilers  |h [electronic resource] :  |b Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings /  |c edited by Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer. 
250 |a 1st ed. 2008. 
264 1 |a Berlin, Heidelberg :  |b Springer Berlin Heidelberg :  |b Imprint: Springer,  |c 2008. 
300 |a XIII, 400 p.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
490 1 |a Theoretical Computer Science and General Issues ;  |v 4917 
490 1 |a Springer eBook Collection 
505 0 |a Invited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable - ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache. 
590 |a Loaded electronically. 
590 |a Electronic access restricted to members of the Holy Cross Community. 
650 0 |a Arithmetic and logic units, Computer. 
650 0 |a Programming languages (Electronic computers). 
650 0 |a Architecture, Computer. 
650 0 |a Microprocessors. 
650 0 |a Input-output equipment (Computers). 
650 0 |a Logic design. 
690 |a Electronic resources (E-books) 
700 1 |a Stenström, Per.  |e editor.  |0 (orcid)0000-0002-7441-8245  |1 https://orcid.org/0000-0002-7441-8245  |4 edt  |4 http://id.loc.gov/vocabulary/relators/edt 
700 1 |a Dubois, Michel.  |e editor.  |4 edt  |4 http://id.loc.gov/vocabulary/relators/edt 
700 1 |a Katevenis, Manolis.  |e editor.  |4 edt  |4 http://id.loc.gov/vocabulary/relators/edt 
700 1 |a Gupta, Rajiv.  |e editor.  |4 edt  |4 http://id.loc.gov/vocabulary/relators/edt 
700 1 |a Ungerer, Theo.  |e editor.  |4 edt  |4 http://id.loc.gov/vocabulary/relators/edt 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
830 0 |a Theoretical Computer Science and General Issues ;  |v 4917 
830 0 |a Springer eBook Collection. 
856 4 0 |u https://holycross.idm.oclc.org/login?auth=cas&url=https://doi.org/10.1007/978-3-540-77560-7  |3 Click to view e-book  |t 0 
907 |a .b33054113  |b 04-18-22  |c 02-26-20 
998 |a he  |b 02-26-20  |c m  |d @   |e -  |f eng  |g gw   |h 0  |i 1 
912 |a ZDB-2-SCS 
912 |a ZDB-2-LNC 
950 |a Computer Science (Springer-11645) 
902 |a springer purchased ebooks 
903 |a SEB-COLL 
945 |f  - -   |g 1  |h 0  |j  - -   |k  - -   |l he   |o -  |p $0.00  |q -  |r -  |s b   |t 38  |u 0  |v 0  |w 0  |x 0  |y .i22185732  |z 02-26-20 
999 f f |i cffa6bfb-6bd4-5b44-a427-19a0eb0ce0e1  |s ed28872b-c586-555a-932a-16f3da92953d  |t 0 
952 f f |p Online  |a College of the Holy Cross  |b Main Campus  |c E-Resources  |d Online  |t 0  |e E-Book  |h Library of Congress classification  |i Elec File