|
|
|
|
| LEADER |
00000nam a22000005i 4500 |
| 001 |
b3305797 |
| 003 |
MWH |
| 005 |
20191024132109.0 |
| 007 |
cr nn 008mamaa |
| 008 |
100301s2008 xxu| s |||| 0|eng d |
| 020 |
|
|
|a 9780387764740
|
| 024 |
7 |
|
|a 10.1007/978-0-387-76474-0
|2 doi
|
| 035 |
|
|
|a (DE-He213)978-0-387-76474-0
|
| 050 |
|
4 |
|a E-Book
|
| 072 |
|
7 |
|a TJFC
|2 bicssc
|
| 072 |
|
7 |
|a TEC008010
|2 bisacsh
|
| 072 |
|
7 |
|a TJFC
|2 thema
|
| 100 |
1 |
|
|a Mohanty, Saraju P.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
|
| 245 |
1 |
0 |
|a Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
|h [electronic resource] /
|c by Saraju P. Mohanty, Nagarajan Ranganathan, Elias Kougianos, Priyardarsan Patra.
|
| 250 |
|
|
|a 1st ed. 2008.
|
| 264 |
|
1 |
|a New York, NY :
|b Springer US :
|b Imprint: Springer,
|c 2008.
|
| 300 |
|
|
|a XXXII, 302 p. 20 illus.
|b online resource.
|
| 336 |
|
|
|a text
|b txt
|2 rdacontent
|
| 337 |
|
|
|a computer
|b c
|2 rdamedia
|
| 338 |
|
|
|a online resource
|b cr
|2 rdacarrier
|
| 347 |
|
|
|a text file
|b PDF
|2 rda
|
| 490 |
1 |
|
|a Springer eBook Collection
|
| 505 |
0 |
|
|a High-Level Synthesis Fundamentals -- Power Modeling and Estimation at Transistor and Logic Gate Levels -- Architectural Power Modeling and Estimation -- Power Reduction Fundamentals -- Energy or Average Power Reduction -- Peak Power Reduction -- Transient Power Reduction -- Leakage Power Reduction -- Conclusions and Future Direction.
|
| 520 |
|
|
|a Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level. At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation. The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including: • Power Reduction Fundamentals • Energy or Average Power Reduction • Peak Power Reduction • Transient Power Reduction • Leakage Power Reduction Low-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.
|
| 590 |
|
|
|a Loaded electronically.
|
| 590 |
|
|
|a Electronic access restricted to members of the Holy Cross Community.
|
| 650 |
|
0 |
|a Electronic circuits.
|
| 650 |
|
0 |
|a Electronics.
|
| 650 |
|
0 |
|a Microelectronics.
|
| 650 |
|
0 |
|a Computer-aided engineering.
|
| 650 |
|
0 |
|a Computer hardware.
|
| 650 |
|
0 |
|a Electrical engineering.
|
| 690 |
|
|
|a Electronic resources (E-books)
|
| 700 |
1 |
|
|a Ranganathan, Nagarajan.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
|
| 700 |
1 |
|
|a Kougianos, Elias.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
|
| 700 |
1 |
|
|a Patra, Priyardarsan.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
|
| 710 |
2 |
|
|a SpringerLink (Online service)
|
| 773 |
0 |
|
|t Springer eBooks
|
| 830 |
|
0 |
|a Springer eBook Collection.
|
| 856 |
4 |
0 |
|u https://holycross.idm.oclc.org/login?auth=cas&url=https://doi.org/10.1007/978-0-387-76474-0
|3 Click to view e-book
|t 0
|
| 907 |
|
|
|a .b33057977
|b 04-18-22
|c 02-26-20
|
| 998 |
|
|
|a he
|b 02-26-20
|c m
|d @
|e -
|f eng
|g xxu
|h 0
|i 1
|
| 912 |
|
|
|a ZDB-2-ENG
|
| 950 |
|
|
|a Engineering (Springer-11647)
|
| 902 |
|
|
|a springer purchased ebooks
|
| 903 |
|
|
|a SEB-COLL
|
| 945 |
|
|
|f - -
|g 1
|h 0
|j - -
|k - -
|l he
|o -
|p $0.00
|q -
|r -
|s b
|t 38
|u 0
|v 0
|w 0
|x 0
|y .i22189592
|z 02-26-20
|
| 999 |
f |
f |
|i 21dd10fc-d114-51da-8d13-fd8a5a5fc4c9
|s 857a031c-d241-5aae-a321-c274e8b76e4e
|t 0
|
| 952 |
f |
f |
|p Online
|a College of the Holy Cross
|b Main Campus
|c E-Resources
|d Online
|t 0
|e E-Book
|h Library of Congress classification
|i Elec File
|