A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof

A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof / by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul.

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The...

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Bibliographic Details
Main Authors: Kovalev, Mikhail (Author), Müller, Silvia M. (Author), Paul, Wolfgang J. (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: Cham : Springer International Publishing : Imprint: Springer, 2014.
Edition:1st ed. 2014.
Series:Theoretical Computer Science and General Issues ; 9000
Springer eBook Collection.
Subjects:
Algorithms.
Software engineering.
Computer hardware.
Microprocessors.
Computer communication systems.
Programming languages (Electronic computers).
Electronic resources (E-books)
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Call Number: E-Book
Status: Available

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