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160827s2016 enk ob 001 0 eng d |
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|a EBLCP
|b eng
|e pn
|c EBLCP
|d N$T
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|a 957156987
|a 957615380
|a 959274959
|a 959536711
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|a 9781119006558
|q (electronic bk.)
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|a 1119006554
|q (electronic bk.)
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|z 9781119006558
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|z 1119006554
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|z 9781119006589
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|z 1119006589
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|z 9781848217386
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|z 1848217382
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|a (OCoLC)957437229
|z (OCoLC)957156987
|z (OCoLC)957615380
|z (OCoLC)959274959
|z (OCoLC)959536711
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|a TK7870.25
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|a TEC
|x 009070
|2 bisacsh
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|a HCDD
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1 |
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|a Fanet, Hervé,
|e author.
|1 https://id.oclc.org/worldcat/entity/E39PCjBVPtfmMVFq6PmQRhQXMK
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|a Ultra low power electronics and adiabatic solutions /
|c Hervé Fanet.
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260 |
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|a Hoboken :
|b Wiley,
|c 2016.
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|a 1 online resource
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336 |
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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|a online resource
|b cr
|2 rdacarrier
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490 |
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|a Electronics engineering series
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504 |
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|a Includes bibliographical references and index.
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588 |
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|a Online resource, title from PDF title page (EBSCO, viewed October 3, 2016).
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|a Cover -- Title Page -- Copyright -- Contents -- Introduction -- 1. Dissipation Sources in Electronic Circuits -- 1.1. Brief description of logic types -- 1.1.1. Boolean logic -- 1.1.2. Combinational and sequential logic -- 1.1.3. NMOS and PMOS transistors -- 1.1.4. Complementary CMOS logic -- 1.1.5. Pass-transistor logic -- 1.1.6. Dynamic logic -- 1.2. Origins of heat dissipation in circuits -- 1.2.1. Joule effect in circuits -- 1.2.2. Calculating dynamic power -- 1.2.3. Calculating static power and its origins -- 2. Thermodynamics and Information Theory -- 2.1. Recalling the basics: entropy and information -- 2.1.1. Statistical definition of entropy -- 2.1.2. Macroscopic energy and entropy -- 2.1.3. Thermostat exchange, Boltzmann's law and the equal division of energy -- 2.1.4. Summary and example of energy production in a conductor carrying a current -- 2.1.5. Information and the associated entropy -- 2.2. Presenting Landauer's principle -- 2.2.1. Presenting Landauer's principle and other examples -- 2.2.2. Experimental validations of Landauer's principle -- 2.3. Adiabaticity and reversibility -- 2.3.1. Adiabatic principle of charging capacitors -- 2.3.2. Adiabaticity and reversibility: a circuit approach -- 3. Transistor Models in CMOS Technology -- 3.1. Reminder on semiconductor properties -- 3.1.1. State densities and semiconductor properties -- 3.1.2. Currents in a semiconductor -- 3.1.3. Contact potentials -- 3.1.4. Metal-oxide semiconductor structure -- 3.1.5. Weak and strong inversion -- 3.2. Long- and short-channel static models -- 3.2.1. Basic principle and brief history of semiconductor technology -- 3.2.2. Transistor architecture and Fermi pseudo-potentials -- 3.2.3. Calculating the current in a long-channel static regime -- 3.2.4. Calculating the current in a short-channel regime -- 3.3. Dynamic transistor models.
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|a 3.3.1. Quasi-static regime -- 3.3.2. Dynamic regime -- 3.3.3. "Small signals" transistor model -- 4. Practical and Theoretical Limits of CMOS Technology -- 4.1. Speed-dissipation trade-off and limits of CMOS technology -- 4.1.1. From the transistor to the integrated circuit -- 4.1.2. Trade-off between speed and consumption -- 4.1.3. The trade-off between dynamic consumption and static consumption -- 4.2. Sub-threshold regimes -- 4.2.1. Recall of the weak inversion properties -- 4.2.2. Limits to sub-threshold CMOS technology -- 4.3. Practical and theoretical limits in CMOS technology -- 4.3.1. Economic considerations and evolving methodologies -- 4.3.2. Technological difficulties: dissipation, variability and interconnects -- 4.3.3. Theoretical limits and open questions -- 5. Very Low Consumption at System Level -- 5.1. The evolution of power management technologies -- 5.1.1. Basic techniques for reducing dynamic power -- 5.1.2. Basic techniques for reducing static power -- 5.1.3. Designing in 90, 65 and 45 nm technology -- 5.2. Sub-threshold integrated circuits -- 5.2.1. Sub-threshold circuit features -- 5.2.2. Pipeline and parallelization -- 5.2.3. New SRAM structure -- 5.3. Near-threshold circuits -- 5.3.1. Optimization method -- 5.4. Chip interconnect and networks -- 5.4.1. Dissipation in the interconnect -- 5.4.2. Techniques for reducing dissipation in the interconnect -- 6. Reversible Computing and Quantum Computing -- 6.1. The basis for reversible computing -- 6.1.1. Introduction -- 6.1.2. Group structure of reversible gates -- 6.1.3. Conservative gates, linearity and affinity -- 6.1.4. Exchange gates -- 6.1.5. Control gates -- 6.1.6. Two basic theorems: "no fan-out" and "no cloning" -- 6.2. A few elements for synthesizing a function -- 6.2.1. The problem and constraints on synthesis -- 6.2.2. Synthesizing a reversible function.
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|a 6.2.3. Synthesizing an irreversible function -- 6.2.4. The adder example -- 6.2.5. Hardware implementation of reversible gates -- 6.3. Reversible computing and quantum computing -- 6.3.1. Principles of quantum computing -- 6.3.2. Entanglement -- 6.3.3. A few examples of quantum gates -- 6.3.4. The example of Grover's algorithm -- 7. Quasi-adiabatic CMOS Circuits -- 7.1. Adiabatic logic gates in CMOS -- 7.1.1. Implementing the principles of optimal charge and adiabatic pipeline -- 7.1.2. ECRL and PFAL in CMOS -- 7.1.3. Comparison to other gate technologies -- 7.2. Calculation of dissipation in an adiabatic circuit -- 7.2.1. Calculation in the normal regime -- 7.2.2. Calculation in sub-threshold regimes -- 7.3. Energy-recovery supplies and their contribution to dissipation -- 7.3.1. Capacitor-based supply -- 7.3.2. Inductance-based supply -- 7.4. Adiabatic arithmetic architecture -- 7.4.1. Basic principles -- 7.4.2. Adder example -- 7.4.3. The interest in complex gates -- 8. Micro-relay Based Technology -- 8.1. The physics of micro-relays -- 8.1.1. Different computing technologies -- 8.1.2. Different actuation technologies -- 8.1.3. Dynamic modeling of micro-electro-mechanical relays -- 8.1.4. Implementation examples and technological difficulties -- 8.2. Calculation of dissipation in a micro-relay based circuit -- 8.2.1. Optimization of micro-relays through electrostatic actuati -- 8.2.2. Adiabatic regime solutions -- 8.2.3. Comparison between CMOS logic and micro-relays -- Bibliography -- Index -- Other titles from iSTE in Electronics Engineering -- EULA.
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|a Electronic apparatus and appliances
|x Cooling.
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|a Power electronics
|x Design and construction.
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|a Low voltage systems
|x Design and construction.
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|a TECHNOLOGY & ENGINEERING
|x Mechanical.
|2 bisacsh
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|a Electronic apparatus and appliances
|x Cooling
|2 fast
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|a Low voltage systems
|x Design and construction
|2 fast
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|a Power electronics
|x Design and construction
|2 fast
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|i has work:
|a Ultra low power electronics and adiabatic solutions (Text)
|1 https://id.oclc.org/worldcat/entity/E39PCFQGvfQHGrjF6jHJDKQYHd
|4 https://id.oclc.org/worldcat/ontology/hasWork
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776 |
0 |
8 |
|i Print version:
|a Fanet, Hervé.
|t Ultra low power electronics and adiabatic solutions.
|d Hoboken : Wiley, 2016
|z 9781848217386
|z 1848217382
|w (OCoLC)885229439
|
830 |
|
0 |
|a Electronics engineering series (London, England)
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856 |
4 |
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|u https://ebookcentral.proquest.com/lib/holycrosscollege-ebooks/detail.action?docID=4648723
|y Click for online access
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|a EBC-AC
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994 |
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|a 92
|b HCD
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