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OCoLC |
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20240623213015.0 |
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cr cnu---unuuu |
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230311s2023 sz ob 001 0 eng d |
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|a EBLCP
|b eng
|e rda
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|d GW5XE
|d YDX
|d EBLCP
|d UKAHL
|d OCLCF
|d OCLCQ
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|a 1371474615
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|a 9783031212949
|q (electronic bk.)
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|a 3031212940
|q (electronic bk.)
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|z 3031212932
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|z 9783031212932
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7 |
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|a 10.1007/978-3-031-21294-9
|2 doi
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|a (OCoLC)1371756035
|z (OCoLC)1371474615
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|a TK7874
|b .U45 2023
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|a TJFC
|2 bicssc
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|a TEC008010
|2 bisacsh
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|a TJFC
|2 thema
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| 049 |
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|a HCDD
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| 100 |
1 |
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|a Ullah, Salim,
|e author.
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| 245 |
1 |
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|a Approximate arithmetic circuit architectures for FPGA-based systems /
|c Salim Ullah, Akash Kumar.
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| 264 |
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1 |
|a Cham :
|b Springer,
|c [2023]
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| 300 |
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|a 1 online resource (190 p.)
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| 336 |
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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| 338 |
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|a online resource
|b cr
|2 rdacarrier
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| 520 |
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|a This book presents various novel architectures for FPGA-optimized accurate and approximate operators, their detailed accuracy and performance analysis, various techniques to model the behavior of approximate operators, and thorough application-level analysis to evaluate the impact of approximations on the final output quality and performance metrics. As multiplication is one of the most commonly used and computationally expensive operations in various error-resilient applications such as digital signal and image processing and machine learning algorithms, this book particularly focuses on this operation. The book starts by elaborating on the various sources of error resilience and opportunities available for approximations on various layers of the computation stack. It then provides a detailed description of the state-of-the-art approximate computing-related works and highlights their limitations. Provides architectures of approximate arithmetic circuits optimized for FPGA-based systems; Describes a methodology for implementing application-specific approximate circuits; Introduces technique for concurrent utilization of approximation knobs.
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| 504 |
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|a Includes bibliographical references and index.
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| 588 |
0 |
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|a Online resource; title from PDF title page (SpringerLink, viewed March 16, 2023).
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| 505 |
0 |
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|a Intro -- Preface -- Acknowledgments -- Contents -- Acronyms -- 1 Introduction -- 1.1 Introduction -- 1.2 Inherent Error Resilience of Applications -- 1.3 Approximate Computing Paradigm -- 1.3.1 Error-Resilient Computing -- 1.3.2 Stochastic Computing -- 1.3.3 Approximate Computing -- 1.3.4 Software Layer Approximation -- 1.3.5 Architecture Layer Approximation -- 1.3.6 Circuit Layer Approximation -- 1.4 Problem Statement -- 1.4.1 Research Challenge -- 1.5 Focus of the Book -- 1.6 Key Contributions and Book Overview -- References -- 2 Preliminaries -- 2.1 Introduction
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| 505 |
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|a 2.2 Xilinx FPGA Slice Structure -- 2.3 Multiplication Algorithms -- 2.3.1 Baugh-Wooley's Multiplication Algorithm -- 2.3.2 Booth's Multiplication Algorithm -- 2.3.3 Sign Extension for Booth's Multiplier -- 2.4 Statistical Error Metrics -- 2.5 Design Space Exploration and Optimization Techniques -- 2.5.1 Genetic Algorithm -- 2.5.2 Bayesian Optimization -- 2.6 Artificial Neural Networks -- References -- 3 Accurate Multipliers -- 3.1 Introduction -- 3.2 Contributions -- 3.3 Related Work -- 3.4 Unsigned Multiplier Architecture -- 3.5 Motivation for Signed Multipliers
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|a 3.6 Baugh-Wooley's Multiplier: Mult-BW -- 3.7 Booth's Algorithm-Based Signed Multipliers -- 3.7.1 Booth-Mult Design -- 3.7.2 Booth-Opt Design -- 3.7.3 Booth-Par Design -- 3.7.3.1 Optimizing Critical Path Delay -- 3.7.3.2 Accumulation of Generated Partial Products -- 3.8 Constant Multipliers -- 3.9 Results and Discussion -- 3.9.1 Experimental Setup and Tool Flow -- 3.9.2 Performance Comparison of the Proposed Accurate Unsigned Multiplier Acc -- 3.9.3 Performance Comparison of the Proposed Accurate Signed Multiplier with the State-of-the-Art Accurate Multipliers
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| 505 |
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|a 3.9.4 Performance Comparison of the Proposed Constant Multiplier with the State-of-the-Art AccurateMultipliers -- 3.10 Conclusion -- References -- 4 Approximate Multipliers -- 4.1 Introduction -- Contributions -- 4.2 Related Work -- 4.3 Unsigned Approximate Multipliers -- 4.3.1 Approximate 44 Multiplier: Approx-1 -- 4.3.2 Approximate 44 Multiplier: Approx-2 -- 4.3.2.1 Approximate 42 Multiplier -- 4.3.2.2 Approx-2 Design -- 4.3.3 Approximate 44 Multiplier: Approx-3 -- 4.4 Designing Higher-Order Approximate Unsigned Multipliers
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|a 4.4.1 Accurate Adders for Implementing 88 Approximate Multipliers from 44 Approximate Multipliers -- 4.4.2 Approximate Adders for Implementing Higher-order Approximate Multipliers -- 4.5 Approximate Signed Multipliers: Booth-Approx -- 4.6 Results and Discussion -- 4.6.1 Experimental Setup and Tool Flow -- 4.6.2 Evaluation of the Proposed Approximate Unsigned Multipliers -- 4.6.2.1 Performance Characterization of Designed Multipliers -- 4.6.2.2 Error Analysis of Proposed Approximate Multipliers
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| 650 |
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|a Integrated circuits
|x Design and construction.
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| 650 |
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0 |
|a Field programmable gate arrays.
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| 650 |
|
7 |
|a Field programmable gate arrays
|2 fast
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| 650 |
|
7 |
|a Integrated circuits
|x Design and construction
|2 fast
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| 700 |
1 |
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|a Kumar, Akash,
|e author.
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| 776 |
0 |
8 |
|i Print version:
|a Ullah, Salim
|t Approximate Arithmetic Circuit Architectures for FPGA-Based Systems
|d Cham : Springer International Publishing AG,c2023
|z 9783031212932
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| 856 |
4 |
0 |
|u https://holycross.idm.oclc.org/login?auth=cas&url=https://link.springer.com/10.1007/978-3-031-21294-9
|y Click for online access
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| 903 |
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|a SPRING-ALL2023
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| 994 |
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|a 92
|b HCD
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