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|a 9781475767063
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|a 10.1007/978-1-4757-6706-3
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|a (DE-He213)978-1-4757-6706-3
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|a Hamdioui, Said.
|e author.
|4 aut
|4 http://id.loc.gov/vocabulary/relators/aut
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|a Testing Static Random Access Memories
|h [electronic resource] :
|b Defects, Fault Models and Test Patterns /
|c by Said Hamdioui.
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| 250 |
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|a 1st ed. 2004.
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| 264 |
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1 |
|a New York, NY :
|b Springer US :
|b Imprint: Springer,
|c 2004.
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| 300 |
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|a XX, 221 p.
|b online resource.
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|a text
|b txt
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|a computer
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| 490 |
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|a Frontiers in Electronic Testing,
|x 0929-1296 ;
|v 26
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| 490 |
1 |
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|a Springer eBook Collection
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| 505 |
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|a I Introductory -- 1 Introduction -- 2 Semiconductor memory architecture -- 3 Space of memory faults -- 4 Preparation for circuit simulation -- II Testing single-port and two-port SRAMs -- 5 Experimental analysis of two-port SRAMs -- 6 Tests for single-port and two-port SRAMs -- 7 Testing restricted two-port SRAMs -- III Testing p-port SRAMs -- 8 Experimental analysis of p-port SRAMs -- 9 Tests for p-port SRAMs -- 10 Testing restricted p-port SRAMs -- 11 Trends in embedded memory testing -- A Simulation results for two-port SRAMs -- A.1 Simulation results for opens -- A.2 Simulation results for shorts -- A.3 Simulation results for bridges -- B Simulation results for three-port SRAMs -- B.1 Simulation results for opens and shorts -- B.2 Simulation results for bridges.
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|a Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed. Features: -Fault primitive based analysis of memory faults, -A complete framework of and classification memory faults, -A systematic way to develop optimal and high quality memory test algorithms, -A systematic way to develop test patterns for any multi-port SRAM, -Challenges and trends in embedded memory testing.
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|a Loaded electronically.
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|a Electronic access restricted to members of the Holy Cross Community.
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|a Electronic circuits.
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|a Electrical engineering.
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| 650 |
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|a Materials science.
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| 650 |
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|a Optical materials.
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|a Electronic materials.
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| 690 |
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|a Electronic resources (E-books)
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|a SpringerLink (Online service)
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| 830 |
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|a Frontiers in Electronic Testing,
|x 0929-1296 ;
|v 26
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| 830 |
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|a Springer eBook Collection.
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| 856 |
4 |
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|u https://holycross.idm.oclc.org/login?auth=cas&url=https://doi.org/10.1007/978-1-4757-6706-3
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