Formal Equivalence Checking and Design Debugging

Formal Equivalence Checking and Design Debugging by Shi-Yu Huang, Kwang-Ting (Tim) Cheng.

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to...

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Bibliographic Details
Main Authors: Shi-Yu Huang (Author), Kwang-Ting (Tim) Cheng (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 1998.
Edition:1st ed. 1998.
Series:Frontiers in Electronic Testing, 12
Springer eBook Collection.
Subjects:
Electronic circuits.
Artificial intelligence.
Electrical engineering.
Computer-aided engineering.
Electronic resources (E-books)
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Call Number: E-Book
Status: Available

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