VHDL Modeling for Digital Design Synthesis

VHDL Modeling for Digital Design Synthesis by Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin.

The purpose of this book is to introduce VHSIC Hardware Description Lan­ guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early sta...

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Bibliographic Details
Main Authors: Yu-Chin Hsu (Author), Tsai, Kevin F. (Author), Liu, Jessie T. (Author), Lin, Eric S. (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 1995.
Edition:1st ed. 1995.
Series:Springer eBook Collection.
Subjects:
Computers.
Engineering.
Electronic circuits.
Computer-aided engineering.
Electrical engineering.
Electronic resources (E-books)
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.
Table of Contents:
  • 1 Introduction
  • 1.1 Design Process
  • 1.2 Levels of Abstraction
  • 1.3 Design Tools
  • 1.4 VHSIC Hardware Description Languages
  • 1.5 Simulation
  • 1.6 Synthesis
  • 1.7 Summary
  • 2 Basic Structures in VHDL
  • 2.1 Entity Declarations
  • 2.2 Architectures
  • 2.3 Packages
  • 2.4 Configurations
  • 2.5 Design Libraries
  • 2.6 Summary
  • 3 Types, Operators and Expressions
  • 3.1 Data Objects
  • 3.2 Data Types
  • 3.3 Operators
  • 3.4 Operands
  • 3.5 Summary
  • 4 Sequential Statements
  • 4.1 Variable Assignment Statements
  • 4.2 Signal Assignment Statements
  • 4.3 If Statements
  • 4.4 Case Statements
  • 4.5 Null Statements
  • 4.6 Assertion Statements
  • 4.7 Loop Statements
  • 4.8 Next Statements
  • 4.9 Exit Statements
  • 4.10 Wait Statements
  • 4.11 Procedure Calls
  • 4.12 Return Statements
  • 4.13 Summary
  • 5 Concurrent Statements
  • 5.1 Process Statements
  • 5.2 Concurrent Signal Assignments
  • 5.3 Conditional Signal Assignments
  • 5.4 Selected Signal Assignments
  • 5.5 Block Statements
  • 5.6 Concurrent Procedure Calls
  • 5.7 Concurrent Assertion Statements
  • 5.8 Summary
  • 6 Subprograms and Packages
  • 6.1 Subprograms
  • 6.2 Packages
  • 6.3 Summary
  • 7 Modeling at the Structural Level
  • 7.1 Component Declarations
  • 7.2 Component Instantiations
  • 7.3 Generate Statements
  • 7.4 Default Bindings
  • 7.5 Configuration Specifications
  • 7.6 Configuration Declarations
  • 7.7 Modeling a Test Bench
  • 7.8 Summary
  • 8 Modeling at the RT Level
  • 8.1 Combinational Logic
  • 8.2 Latches
  • 8.3 Designs with Two Phase Clocks
  • 8.4 Flip-Flops
  • 8.5 Synchronous Sets And Resets
  • 8.6 Asynchronous Sets And Resets
  • 8.7 VHDL Templates for RTL circuits
  • 8.8 Registers
  • 8.9 Asynchronous Counters
  • 8.10 Synchronous Counters
  • 8.11 Tri-State Buffers
  • 8.12 Busses
  • 8.13 Netlist of RTL Components
  • 8.14 Summary
  • 9 Modeling at the FSMD Level
  • 9.1 Moore Machines
  • 9.2 Asynchronous Mealy Machines
  • 9.3 Synchronous Mealy Machines
  • 9.4 Separation of FSM and Datapath
  • 9.5 An FSM with a Datapath (FSMD)
  • 9.6 Communicating FSMs
  • 9.7 Summary
  • 10 Modeling at the Algorithmic Level
  • 10.1 Process and Architecture
  • 10.2 Wait Statements
  • 10.3 Synchronous Reset
  • 10.4 Asynchronous Reset
  • 10.5 Registers and Counters
  • 10.6 Simple Sequential Circuits
  • 10.7 Algorithms
  • 10.8 Process Communication
  • 10.9 Summary
  • 11 Memories
  • 11.1 Memory Read/Write at the RT Level
  • 11.2 Memory Inference at the Algorithmic Level
  • 11.3 Summary
  • 12 VHDL Synthesis
  • 12.1 VHDL Design Descriptions
  • 12.2 Constraints
  • 12.3 Technology Library
  • 12.4 Delay Calculation
  • 12.5 The Synthesis Tool
  • 12.6 Design Space Exploration
  • 12.7 Synthesis Directives
  • 12.8 Summary
  • 13 Writing Efficient VHDL Descriptions
  • 13.1 Software to Hardware Mapping
  • 13.2 Variables and Signals
  • 13.3 Using minimum bit width
  • 13.4 Using effective algorithms
  • 13.5 Sharing complex operators using module functions
  • 13.6 Specifying don’t care conditions
  • 13.7 Writing low level code
  • 13.8 Summary
  • 14 Practicing Designs
  • 14.1 Bit Clock Generator
  • 14.2 Traffic Light Controller
  • 14.3 Vending Machine
  • 14.4 Black Jack Dealer Machine
  • 14.5 Designing a Stack Computer
  • References.

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