Formal Semantics for VHDL

Formal Semantics for VHDL edited by Carlos Delgado Kloos, P. Breuer.

It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several...

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Bibliographic Details
Corporate Author: SpringerLink (Online service)
Other Authors: Delgado Kloos, Carlos (Editor), Breuer, P. (Editor)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 1995.
Edition:1st ed. 1995.
Series:The Springer International Series in Engineering and Computer Science, 307
Springer eBook Collection.
Subjects:
Electronic circuits.
Programming languages (Electronic computers).
Computers.
Computer hardware.
Artificial intelligence.
Electrical engineering.
Electronic resources (E-books)
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Call Number: E-Book
Status: Available

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