Principles of Verifiable RTL Design A functional coding style supporting verification processes in Verilog / by Lionel Bening, Harry D. Foster.
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improveme...
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