Layout Minimization of CMOS Cells

Layout Minimization of CMOS Cells by Robert L. Maziasz, John P. Hayes.

The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer­ aided-design (CAD) programs are required to automate the...

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Bibliographic Details
Main Authors: Maziasz, Robert L. (Author), Hayes, John P. (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 1992.
Edition:1st ed. 1992.
Series:The Springer International Series in Engineering and Computer Science, 160
Springer eBook Collection.
Subjects:
Electrical engineering.
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Call Number: E-Book
Status: Available

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