Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction

Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction / by P. van der Meer, A. van Staveren, Arthur H.M. van Roermund.

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devic...

Full description

Saved in:
Bibliographic Details
Main Authors: van der Meer, P. (Author), van Staveren, A. (Author), van Roermund, Arthur H.M (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 2004.
Edition:1st ed. 2004.
Series:The Springer International Series in Engineering and Computer Science, 841
Springer eBook Collection.
Subjects:
Electrical engineering.
Engineering design.
Computers.
Electronics.
Microelectronics.
Electronic resources (E-books)
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.
Login for hold information

‌

Click to view e-book

Online

Holdings details from Online
Call Number: E-Book
Copy 1 Available

Similar Items