Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction

Low-Power Deep Sub-Micron CMOS Logic Sub-threshold Current Reduction / by P. van der Meer, A. van Staveren, Arthur H.M. van Roermund.

1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devic...

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Bibliographic Details
Main Authors: van der Meer, P. (Author), van Staveren, A. (Author), van Roermund, Arthur H.M (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 2004.
Edition:1st ed. 2004.
Series:The Springer International Series in Engineering and Computer Science, 841
Springer eBook Collection.
Subjects:
Electrical engineering.
Engineering design.
Computers.
Electronics.
Microelectronics.
Electronic resources (E-books)
Online Access:Click to view e-book
Holy Cross Note:Loaded electronically.
Electronic access restricted to members of the Holy Cross Community.
Table of Contents:
  • 1. Introduction
  • 1.1 Power-dissipation trends in CMOS circuits
  • 1.2 Overview of present power-reduction solutions
  • 1.3 Aim and scope of this book
  • 1.4 Organization of the book
  • 2. Power Versus Energy
  • 2.1 Power considerations
  • 2.2 Energy considerations
  • 2.3 Conclusions
  • 3. Power Dissipation in Digital CMOS Circuits
  • 3.1 Thermodynamics of computation
  • 3.2 Functional power dissipation
  • 3.3 Parasitical power dissipation
  • 3.4 Trends in power dissipation
  • 3.5 Conclusions
  • 4. Reduction of Functional Power Dissipation
  • 4.1 Node transition-cycle activity factor
  • 4.2 Clock frequency
  • 4.3 Transition-cycle energy
  • 4.4 Conclusions
  • 5. Reduction of Parasitical Power Dissipation
  • 5.1 Leakage power dissipation
  • 5.2 Short-circuit power dissipation
  • 5.3 Need for weak-inversion current reduction
  • 5.4 Conclusions
  • 6. Weak-Inversion Current Reduction
  • 6.1 Classification
  • 6.2 Conclusions
  • 7. Effectiveness of Weak-Inversion Current Reduction
  • 7.1 General effectiveness
  • 7.2 Technique-specific effectiveness
  • 7.3 Conclusions
  • 8. Triple-S Circuit Designs
  • 8.1 Process flow
  • 8.2 Experimental circuits
  • 8.3 Leakage, speed, area and functional power
  • 8.4 Practical applications and limitations
  • 8.5 Conclusions
  • 9. Conclusions
  • 10. Summary
  • References.

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