Formal Semantics and Proof Techniques for Optimizing VHDL Models

Formal Semantics and Proof Techniques for Optimizing VHDL Models by Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey.

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to r...

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Bibliographic Details
Main Authors: Umamageswaran, Kothanda (Author), Pandey, Sheetanshu L. (Author), Wilsey, Philip A. (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 1999.
Edition:1st ed. 1999.
Series:Springer eBook Collection.
Subjects:
Electronic circuits.
Computer hardware.
Computer-aided engineering.
Electrical engineering.
Electronic resources (E-books)
Online Access:Click to view e-book
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Call Number: E-Book
Status: Available

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