Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms by Gary D. Hachtel, Fabio Somenzi.

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis...

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Bibliographic Details
Main Authors: Hachtel, Gary D. (Author), Somenzi, Fabio (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 1996.
Edition:1st ed. 1996.
Series:Springer eBook Collection.
Subjects:
Electronic circuits.
Computer logic.
Electrical engineering.
Computer-aided engineering.
Computer science—Mathematics.
Artificial intelligence.
Electronic resources (E-books)
Online Access:Click to view e-book
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Call Number: E-Book
Status: Available

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