High Level Synthesis of ASICs under Timing and Synchronization Constraints

High Level Synthesis of ASICs under Timing and Synchronization Constraints by David C. Ku, Giovanni DeMicheli.

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in th...

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Bibliographic Details
Main Authors: Ku, David C. (Author), DeMicheli, Giovanni (Author)
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: New York, NY : Springer US : Imprint: Springer, 1992.
Edition:1st ed. 1992.
Series:The Springer International Series in Engineering and Computer Science, 177
Springer eBook Collection.
Subjects:
Electronic circuits.
Electrical engineering.
Computer-aided engineering.
Electronic resources (E-books)
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Call Number: E-Book
Status: Available

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