Logic synthesis and SOC prototyping : RTL design using VHDL / Vaibbhav Taraate.
This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC perfor...
Full description
Saved in: