ASIC design and synthesis : RTL design using Verilog / Vaibbhav Taraate.

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in...

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Bibliographic Details
Main Author: Taraate, Vaibbhav
Format: Electronic eBook
Language:English
Published: Singapore : Springer, 2021.
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