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|a Taraate, Vaibbhav.
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|a ASIC design and synthesis :
|b RTL design using Verilog /
|c Vaibbhav Taraate.
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|a Singapore :
|b Springer,
|c 2021.
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| 300 |
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|a 1 online resource
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|a text
|b txt
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|a online resource
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|a text file
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|a Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Introduction -- 1.1 ASIC Design -- 1.2 Types of ASIC -- 1.3 Abstraction Levels -- 1.4 Design Examples -- 1.5 What We Should Know? -- 1.6 Important Terms Used Throughout Design Cycle -- 1.7 Chapter Summary -- 2 ASIC Design Flow -- 2.1 ASIC Design Flow -- 2.1.1 Logic Design -- 2.1.2 Physical Design -- 2.2 FPGA Design Flow -- 2.3 Examples and Thought Process -- 2.4 Design Challenges -- 2.5 Chapter Summary -- 3 Let Us Build Design Foundation -- 3.1 Combinational Design Elements
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|a 3.2 Logic Understanding and Use of Construct -- 3.3 Arithmetic Resources and Area -- 3.4 Code Converter -- 3.4.1 Binary to Gray Code Converter -- 3.4.2 Gray to Binary Code Converter -- 3.5 Multiplexers -- 3.6 Cascading Stages of MUX Using Instantiation -- 3.7 Decoders -- 3.8 Encoders -- 3.9 Priority Encoders -- 3.10 Strategies During ASIC Design -- 3.11 Exercises -- 3.12 Chapter Summary -- 4 Sequential Design Concepts -- 4.1 Sequential Design Elements -- 4.2 Let Us Understand Blocking Versus Non-blocking Assignments -- 4.2.1 Blocking Assignments -- 4.2.2 Reordering of the Blocking Assignments
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|a 4.2.3 Non-blocking Assignments -- 4.2.4 Reordering of the Non-blocking Assignments -- 4.3 Latch-Based Designs -- 4.4 Flip-Flop-Based Designs -- 4.5 Reset Strategies -- 4.5.1 Asynchronous Reset -- 4.5.2 Synchronous Reset -- 4.6 Frequency Divider -- 4.7 Synchronous Design -- 4.8 Asynchronous Design -- 4.9 RTL Design and Verification for Complex Designs -- 4.10 Exercises -- 4.11 Chapter Summary -- 5 Important Design Considerations -- 5.1 Timing Parameters -- 5.2 Metastability -- 5.3 Clock Skew -- 5.3.1 Positive Clock Skew -- 5.3.2 Negative Clock Skew -- 5.4 Slack -- 5.4.1 Setup Slack
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|a 5.4.2 Hold Slack -- 5.5 Clock Latency -- 5.6 Area for the Design -- 5.7 Speed Requirements -- 5.8 Power Requirements -- 5.9 What Are Design Constraints? -- 5.10 Exercises -- 5.11 Chapter Summary -- 6 Important Considerations for ASIC Designs -- 6.1 Synchronous Design and Considerations -- 6.2 Positive Clock Skew and Impact on Speed -- 6.3 Negative Clock Skew and Impact on the Speed -- 6.4 Clock and Network Latency -- 6.5 Timing Paths in the Design -- 6.5.1 Input to Reg Path -- 6.5.2 Reg to Output Path -- 6.5.3 Reg to Reg Path -- 6.5.4 Input to Output Path -- 6.6 Frequency Calculations
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|a 6.7 What Is On-Chip Variations -- 6.8 Exercises -- 6.9 Chapter Summary -- 7 Multiple Clock Domain Designs -- 7.1 General Strategies for Multiple Clock Domain Designs -- 7.2 What Are Issues in the Multiple Clock Domain Design -- 7.3 Architecture Design Strategies -- 7.4 Control Path and Synchronization -- 7.4.1 Level or Multiflop Synchronizer -- 7.4.2 Pulse Synchronizers -- 7.4.3 MUX Synchronizer -- 7.5 Challenges in the Multiple Bit Data Transfer -- 7.6 Data Path Synchronizers -- 7.6.1 Handshaking Mechanism -- 7.6.2 FIFO Synchronizer -- 7.6.3 Gray Encoding -- 7.7 Summary and Future Discussions
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|a This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
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| 504 |
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|a Includes bibliographical references and index.
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| 650 |
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|a Application-specific integrated circuits
|x Design.
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| 650 |
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|a Verilog (Computer hardware description language)
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| 650 |
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|a Verilog (Computer hardware description language)
|2 fast
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| 650 |
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|a Application-specific integrated circuits
|x Design
|2 fast
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|a Electronic circuits
|2 fast
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|a Logic design
|2 fast
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|a Microprogramming
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|i has work:
|a ASIC DESIGN AND SYNTHESIS (Text)
|1 https://id.oclc.org/worldcat/entity/E39PCYPm7DRBGx4YCRd9g4vpKd
|4 https://id.oclc.org/worldcat/ontology/hasWork
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| 776 |
0 |
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|i Print version:
|a Taraate, Vaibbhav.
|t ASIC design and synthesis.
|d Singapore : Springer, 2021
|z 9813346418
|z 9789813346413
|w (OCoLC)1202752318
|
| 856 |
4 |
0 |
|u https://holycross.idm.oclc.org/login?auth=cas&url=https://link.springer.com/10.1007/978-981-33-4642-0
|y Click for online access
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|a springengine2021
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| 994 |
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|a 92
|b HCD
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